1. Field of the Invention
The present invention relates to a semiconductor memory device employing a hierarchical bit-line structure in which main bit lines are formed above sub-bit lines. More particularly, the present invention relates to a memory cell array configuration of mask ROM (read only memory) and EEPROM (electrically erasable programmable read only memory) which employ a hierarchical bit-line structure.
2. Description of the Related Art
As a conventional example of non-volatile memories such as flash EEPROM and mask ROM (hereinafter, collectively referred to as ROM), there is Japanese Laid-open Publication No. 6-104406, which is assigned to the same assignee as the instant application. Japanese Laid-open Publication No. 6-104406 has proposed a RAM employing a hierarchical bit-line structure.
This conventional ROM will now be described in terms of its configuration with reference to FIGS. 5 and 6. FIG. 5 shows a partial layout pattern of the ROM, and FIG. 6 shows an equivalent circuit thereof.
A plurality of sub-bit lines Sb11, SB12, . . . are provided in the column direction on a semiconductor substrate. The plurality of sub-bit lines are formed from a diffusion layer of a conductivity type which is opposite to a conductivity type of the semiconductor substrate. Moreover, a plurality of word lines WL001, WL101, WL102, . . . are provided in the row direction so as to intersect the plurality of sub-bit lines extend. The plurality of word lines are formed from polysilicon.
A memory cell transistor (hereinafter, simply referred to as a memory cell) such as M1 to M7 is provided between every adjacent two sub-bit lines. For example, the memory cell M1 is provided between the sub-bit lines SB11 and SB12. The word lines serve as the gate electrodes of the corresponding memory cells. Thus, the memory cells are arranged in a matrix on a prescribed region of the semiconductor substrate.
Auxiliary conductive regions BB11, BB12, . . . , BB21, BB22, . . . are formed in the vicinity of the ends of the corresponding sub-bit lines. For example, the auxiliary conductive region BB21 is formed in the vicinity of the ends of the sub-bit line SB11 to SB15 and SB21 to SB25. Each auxiliary conductive region thus formed is of the same conductivity type as that of the sub-bit lines. It should be noted that, in this specification, the term "conductive" means "electrically conductive" unless otherwise mentioned.
Moreover, bank selection transistors (hereinafter, referred to as bank cells) such as BT01 to BT27 are formed in a region between two sub-bit lines which are adjacent to an auxiliary conductive region. For example, bank cells BT11 and BT12 are respectively formed between the sub-bit line SB12 and the auxiliary conductive region BB11, and between the sub-bit line SB14 and the auxiliary conductive region BB11. The sub-bit lines SB12 and SB14 are adjacent to the auxiliary conductive region BB11. A plurality of bank selection lines such as BS01 to BS24 are formed in the row direction, and the bank selection lines serve as the gate electrodes of the corresponding bank cells. The plurality of bank selection lines are formed from polysilicon.
A plurality of main bit lines MBIT1, MBIT2, MBIT3, MBIT4, . . . are provided in the column direction as metal interconnections. Each of the auxiliary conductive regions is connected to a corresponding main bit line through a corresponding contact (such as CT11 to CT22). A set of sub-bit lines extending in parallel to each other and auxiliary conductive regions connected to the sub-bit lines is hereinafter referred to as a bank (such as BANK0, BANK1 and BANK2).
In the above-mentioned conventional ROM, four bank selection lines are required per bank. More specifically, as shown in FIG. 6, the bank cells BT12, BT14, . . . are connected to the bank selection line BS12, whereas the bank cells BT11, BT13, . . . are connected to the bank selection line BS11.
Hereinafter, an operation of the above-mentioned conventional ROM will be described, assuming that the semiconductor substrate is of a P.sup.- -type, and the sub-bit lines and the auxiliary conductive regions are of an N.sup.+ -type.
First, when potentials at a bank selection line and a word line are set to a high level, a bank cell and a memory cell are selected. The gate electrode of each bank cell is formed from a part of a corresponding bank selection line, whereas the gate electrode of each memory cell is formed from a part of a corresponding word line.
A threshold of a memory cell can be set by the amount of boron ions implanted into its channel region which is formed under the gate electrode. In other words, a memory cell which has been subjected to the ion implantation has a higher threshold voltage. Therefore, when the amount of ion implantation is set to a prescribed value, a memory cell which has been subjected to the ion implantation remains in an OFF state even when the gate potential attains a high level (i.e., OFF-cell). In this case, a memory cell which has not been subjected to the ion implantation is turned on in response to the high level of the gate electrode (i.e., ON-cell).
It should be noted that, by the above-mentioned ion implantation, a portion of each bank selection line which does not constitute the bank cells is set to be in an OFF state.
A memory cell in a bank (such as BANK1) is selected by a row selection circuit (not shown). More specifically, the row selection circuit selects the word line and sub-bit lines by setting the word line and the bank selection lines which are connected to the sub-bit lines to a high level. Thus, the memory cell is selected, and data is read from the memory cell thus selected.
For example, data in the memory cell M2 is read as follows: the memory cell M2 in the bank BANK1 is selected by selecting the word line WL131 (i.e., the gate electrode) and the sub-bit lines SB12 and SB13 (i.e., the source and drain) by the row selection circuit. At this time, the row selection circuit selects the word line WL131 and the sub-bit lines SB12 and SB13 by setting to a high level the word line WL131 and the bank selection lines BS11 and BS13, which are connected to the sub-bit lines SB12 and SB13, while setting the other word lines and bank selection lines to a low level. As a result, the bank cells BT11 and BT16 are selected, whereby the memory cell M2 is selected. The sub-bit lines SB12 and SB13 are connected to the auxiliary conductive regions BB11 and BB21 through the bank cells BT11 and BT16, and thus, are connected to the main bit lines MBIT1 and MBIT2 through the contacts CT11 and CT21, respectively. The main bit lines MBIT1 and MBIT2 are selectively connected to respective data lines by a column selection circuit (not shown). Data in the memory cell M2 is read through this data path.
According to the above-mentioned conventional ROM, the plurality of banks BANK1, BANK2, . . . are successively arranged in the column direction with a common auxiliary conductive region therebetween. Moreover, the plurality of sub-bit lines are successively arranged in, the row direction. Thus, the memory cell array is formed.
In each bank, two sub-bit lines are connected to a single main bit line through the corresponding bank cells. In other words, two sub-bit lines are provided per main bit line in each bank. Each pair of sub-bit lines are connected through the corresponding bank cells to the corresponding main bit line on the opposite sides of the bank. More specifically, referring to FIG. 6, the sub-bit line SB12 is connected through the bank cell BT11 to the main bit line MBIT1 on the left side of the bank BANK1, whereas the sub-bit line SB13 is connected through the bank cell BT16 to the main bit line MBIT1 on the right side of the bank BANK1. These two main bit lines are connected to respective data lines through the column selection circuit, wherein one of the data lines is connected to a low potential, whereas the other data line is connected to a high potential. Accordingly, an ON/OFF state of the memory cell of interest can be read by detecting the difference in current between the data lines.
The above-mentioned conventional ROM has a hierarchical bit-line structure. Therefore, among a plurality of sub-bit lines connected to a single main bit line, sub-bit lines other than those associated with a memory cell to be accessed are electrically disconnected from the main bit line by the corresponding bank cells. As a result, a load imposed on the main bit line is reduced, whereby the access speed can be increased.
According to the above-mentioned conventional ROM having a hierarchical bit-line structure, a single main bit line is provided for every two sub-bit lines.
In general, in the upper layers of the semiconductor device, dense interconnections are less likely to be produced, due to the difference in level produced in the semiconductor substrate during the production process. The main bit lines are metal interconnections which are formed of a layer located higher than a buried diffusion layer forming the sub-bit lines. Therefore, the main bit lines is subject to a strict design rule.
Moreover, in order to reduce a resistance of the main bit lines, a width of the main bit lines must be increased.
Furthermore, a selection transistor which constitutes a column selection circuit for selecting one of the main bit lines must be provided on a main bit-line by main bit-line basis. Therefore, the area of the column selection circuit is increased according to an increase in the number of the main bit lines, whereby reduction in size of the ROM is limited.
In order to solve such problems as described above, the number of sub-bit lines connected to a single main bit line may be increased. In this case, the number of main bit lines can be reduced, whereby the design rule for the main bit lines becomes less strict. Therefore, a width of the main bit lines can be increased, while preventing an increase in the area of the column selection circuit.
However, as shown in FIG. 7, in the case where the number of sub-bit lines connected to a single main bit line is increased in the above-mentioned conventional ROM, the number of bank selection lines in each bank is increased corresponding to the increase in the number of the sub-bit lines. As a result, the area of the memory cell array is disadvantageously increased.